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september 2013 rev 3 1/20 1 tda7342 digitally controlled audio processor features ? input multiplexer ? two stereo and one mono inputs ? one quasi differential input ? selectable input gain for optimal adaptation to different sources ? fully programmable loudness function ? volume control in 0.3d b steps including gain up to 20db ? zero crossing mute, soft mute and direct mute ? bass and treble control ? four speaker attenuators ? four independent speakers control in 1.25db steps for balance and fader facilities ? independent mute function ? all functions programmable via serial i 2 c bus description the audioprocessor tda7342 is an upgrade of the tda731x audioprocessor family. due to a highly linear signal processing, using cmos-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained. several new features like softmute, and zero-crossing mute are implemented. the soft mute function can be activated in two ways: 1. via serial bus (mute byte, bit d0) 2. directly on pin 21 through an i/o line of the microcontroller very low dc stepping is obtained by use of a bicmos technology. order codes lqfp32 part number package packing tda7342 lqfp32 tray tda7342tr lqfp32 tape and reel www.st.com
contents tda7342 2/20 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
tda7342 list of tables 3/20 list of tables table 1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. speaker attenuators (lf, lr, rf, rr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. bass/treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
list of figures tda7342 4/20 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. data validity on the i2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. timing diagram of i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. acknowledge on the i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. lqfp32 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
tda7342 block diagram and pin description 5/20 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connection (top view) 13 12 10 11 l1 l2 l3 l1 l2 l3 m 7 8 5 r1 r2 r3 r1 r2 r3 m m cd gnd 6 input selector + gain left inputs cd right inputs supply 30 31 29 zero cross + mute soft mute out(l) in(l) 16 15 loud+ vol zero cross + mute loud+ vol bass bass loud(l) 9 treble treble 10 f c9 314 csm out(r) cref in(r) 2 4 loud(r) bout(l) bin(l) 18 17 bout(r) bin(r) 20 19 1 treble(r) spkr att mute spkr att mute spkr att mute spkr att mute treble(l) 32 23 28 27 26 24 25 22 out left front out left rear scl sda diggnd out right front out right rear d94au104b bus serial bus decoder + latches mono input c1 c2 c6 c3 c7 c8 c4 c5 c10 c12 47nf csm 47nf c14 100nf c15 100nf 4.7k c16 2.7nf c19 2.7nf c18 100nf c17 100nf c13 47nf c11 r2 4.7k 21 sm v s r1 1 2 3 5 6 4 7 8 11 12 13 14 15 16 32 30 31 29 28 27 26 25 19 18 17 24 23 22 20 21 in r2 in r3 loud r in r tr r out r in r1 mono loud l in l3 cd gnd in l2 in l1 csm in l out l tr l v s gnd sm cref scl sda dig gnd bin r bout l bin l out lf out rf out lr bout r out rr d94au105a 910
electrical specifications tda7342 6/20 2 electrical specifications 2.1 absolute maximum ratings 2.2 quick reference data 2.3 thermal data table 1. absolute maximum ratings symbol parameter value unit v s operating supply voltage 10.5 v t amb operating ambient temp erature -40 to 85 ? c t stg storage temperature range -55 to 150 ? c table 2. quick reference data symbol parameter min. typ. max. unit v s supply voltage 6 9 10.2 v v cl max. input signal handling 2.1 2.6 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.08 % s/n signal to noise ratio 106 db s c channel separation 100 db volume control 0.3db step -59.7 20 db treble control 2db step -14 +14 db bass control 2db step -10 +18 db fader and balance control 1.25db step -38.75 0 db input gain 3.75db step 0 11.25 db mute attenuation 100 db table 3. thermal data symbol parameter value unit r th j-amb thermal resistance junction to pins 150 ? c/w
tda7342 electrical specifications 7/20 2.4 electrical characteristics table 4. electrical characteristics (v s = 9v; r l = 10k ? ; r g = 50 ? ; t amb = 25c; all gains = 0db; f = 1khz. refer to the test circuit, unless othe rwise specified.) symbol parameter test condition min. typ. max. unit input selector r i input resistance 70 100 130 k ?? v cl clipping level d ?? 0.3% 2.1 2.6 v rms s i input separation 80 100 db r l output load resistance 2 k ?? g i min minimum input gain -0.75 0 0.75 db g i max maximum input gain 10.25 11.25 12.25 db g step step resolution 2.75 3.75 4.75 db e n input noise 20hz to 20 khz unweighted 2.3 ? v v dc dc steps adiacent gain steps 1.5 10 mv g iin to g imax 3 mv differential in put ( in 3) r i input resistance input selector bit d6 = 0 (0db) 10 15 20 k ?? input selector bit d6 = 1(-6db) 14 20 30 k ?? cmrr common mode rejection ratio v cm = 1v rms ; f =1khz 48 75 db f = 10khz 45 70 db d distortion v i = 1v rms 0.01 0.08 % e in input noise 20hz to 20khz; flat; d6 = 0 5 ? v g diff differential gain d6 = 0 -1 0 1 db d6 = 1 -7 -6 -5 db volume control r i input resistance 35 50 k ?? g max maximum gain 18.75 20 21.25 db a max maximum attenuation 57.7 59.7 62.7 db a stepc step resolution coarse atten. 0.5 1.25 2.0 db a stepf step resolution fine attenuation 0.11 0.31 0.51 db e a attenuation set error g = 20 to -20db -1.25 0 1.25 db g = -20 to -58db -3 2 db e t tracking error 2 db v dc dc steps adiacent attenuation steps -3 0 3 mv from 0db to a max 0.5 5 mv
electrical specifications tda7342 8/20 loudness control r i internal resistor loud = on 35 50 65 k ?? a max maximum attenuation 17.5 18.75 20.0 db a step step resolution 0.5 1.25 2.0 db zero crossing mute v th zero crossing threshold (1) win = 11 20 mv win = 10 40 mv win = 01 80 mv win = 00 160 mv a mute mute attenuation 80 100 db v dc dc step 0db to mute 0 3 mv soft mute a mute mute attenuation 45 60 db t don on delay time c csm = 22nf; 0 to -20db; i = i max 0.7 1 1.7 ms c csm = 22nf; 0 to -20db; i = i min 20 35 55 ms i doff off current v csm = 0v; i = i max 25 50 75 ? a v csm = 0v; i = i min 1 ? a v thsm soft mute threshold (pin 14) 1.5 2.5 3.5 v r int pull-up resistor (pin 21) (2) 35 50 65 k ? v smh (pin 21) level high 3.5 v v sml (pin 21) level low soft mute active 1 v bass control b boost max bass boost 15 18 20 db b cut max bass cut -8.5 -10 -11.5 db a step step resolution 1 2 3 db r g internal feedback resistance 45 65 85 k ?? treble control c range control range ? 13 ? 14 ? 15 db a step step resolution 1 2 3 db speaker attenuators c range control range 35 37.5 40 db a step step resolution 0.5 1.25 2.00 db table 4. electrical characteristics (continued) (v s = 9v; r l = 10k ? ; r g = 50 ? ; t amb = 25c; all gains = 0db; f = 1khz. refer to the test circuit, unless othe rwise specified.) symbol parameter test condition min. typ. max. unit
tda7342 electrical specifications 9/20 a mute output mute attenuation data word = xxx11111 80 100 db e a attenuation set error 1.25 db v dc dc steps adjacent att enuation steps 0 3 mv audio output v clip clipping level d = 0.3% 2.1 2.6 vrms r l output load resistance 2 k ?? r o output impedance 30 100 ? v dc dc voltage level 3.5 3.8 4.1 v general v cc supply voltage 6 9 10.2 v i cc supply current 5 10 15 ma psrr power supply rejection ratio f = 1khz 60 80 db b = 20 to 20khz "a" weighted 65 db e no output noise output muted (b = 20 to 20khz flat) 2.5 ? v all gains 0db (b = 20 to 20khz flat) 5 15 ? v e t total tracking error a v = 0 to -20db 0 1 db a v = -20 to -60db 0 2 db s/n signal to noise ratio all gains = 0db; v o = 1vrms 106 db s c channel separation 80 100 db d distortion v in =1v 0.01 0.08 % bus inputs v il input low voltage 1 v v ln input high voltage 3 v i ln input current v in = 0.4v -5 5 ? a v o output voltage sda acknowledge i o = 1.6ma 0.4 0.8 v 1. win represents the mute programming bit pair d6 , d5 for the zero crossing window threshold. 2. internal pull-up resistor to vs/2; low = softmute active. table 4. electrical characteristics (continued) (v s = 9v; r l = 10k ? ; r g = 50 ? ; t amb = 25c; all gains = 0db; f = 1khz. refer to the test circuit, unless othe rwise specified.) symbol parameter test condition min. typ. max. unit
i2c bus interface tda7342 10/20 3 i 2 c bus interface data transmission from micropro cessor to the tda7342 and viceversa takes place thru the 2 wires i 2 c bus interface, consisting of the two lin es sda and scl (pull-up resistors to positive supply voltage must be externally connected). 3.1 data validity as shown in figure 3 , the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 3.2 start and stop conditions as shown in figure 5 a start condition is a high to low transition of the sda line while scl is high. the stop conditio n is a low to high transition of the sda line while scl is high. a stop conditions must be sent before each start condition. 3.3 byte format every byte transferred to the sda line must cont ain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 3.4 acknowledge the master (p) puts a resistive high leve l on the sda line during the acknowledge clock pulse (see figure 5 ). the peripheral (audioprocessor) that acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line re mains at the high level during the ninth clock pulse time. in this case the master tr ansmitter can generate the stop information in order to abort the transfer. 3.5 transmission without acknowledge avoiding to detect the acknowledge of the audioprocessor, the ? p can use a simplier transmission: simply it wait s one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking and decreases the noise immunity.
tda7342 i2c bus interface 11/20 figure 3. data validity on the i 2 c bus figure 4. timing diagram of i 2 c bus figure 5. acknowledge on the i 2 c bus patent note: purchase of i 2 c components of stmicrolectronics, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. sda scl data line stable, data valid change data allowed d99au1031 scl sda start i 2 cbus stop d99au1032 scl 1 msb 23789 sda start acknowledgment from receiver d99au1033
software specification tda7342 12/20 4 software specification 4.1 interface protocol the interface protocol comprises: ? a start condition (s) ? a chip address byte, (the lsb bit determines read/write transmission) ? a subaddress byte. ? a sequence of data (n-bytes + acknowledge) ? a stop condition (p) figure 6. interface protocol ack = acknowledge s = start p = stop i = auto increment x = not used a= i 2 c address value selectable ac cording to addr pin status addr = open/gnda = o addr = v cc a = i max clock speed 500kbits/s 4.2 auto increment if bit i in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled s 1 0 0 0 1 0 0 r/w ack i ack data ack p msb lsb msb lsb msb lsb chip address d05au1575 xxx a 3 a 2 a 1 a 0 subaddress data 1 ... data n table 5. subaddress (receive mode) msb lsb function x x x i a3 a2 a1 a0 0 0 0 0 input selector 0 0 0 1 loudness 0 0 1 0 volume 0 0 1 1 bass, treble 0 1 0 0 speaker attenuator lf 0 1 0 1 speaker attenuator lr 0 1 1 0 speaker attenuator rf 0 1 1 1 speaker attenuator rr 1 0 0 0 mute
tda7342 software specification 13/20 4.3 transmitted data zm = zero crossing muted (high active) sm = soft mute activated (high active) x = not used the transmitted data is automatically updated after each ack. transmission can be repeated without new chip address. 4.4 data byte specification x = not relevant; set to "1" during testing for example to select the in 2 input with a gain of 7.5db the data byte is: x x 1 0 1 0 0 1 table 6. send mode msb lsb x x x x x sm zm x table 7. input selector msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 0 not used 0 1 0 0 1 in 2 0 1 0 1 0 in 1 0 1 0 1 1 am mono 0 1 1 0 0 not used 0 1 1 0 1 not used 0 1 1 1 0 not allowed 0 1 1 1 1 not allowed 0 1 0 0 11.25db gain 0 1 0 1 7.5db gain 0 1 1 0 3.75db gain 0 1 1 1 0db gain 0 0db differential input gain (in3) 1 -6db differential input gain (in3)
software specification tda7342 14/20 for example to select -17.5db attenuation, loudness off, the data byte is: x x x1 1 1 1 0 table 8. loudness msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 x x x 0 0 0 0 0 0db x x x 0 0 0 0 1 -1.25db x x x 0 0 0 1 0 -2.5db x x x 0 0 0 1 1 -3.75db x x x 0 0 1 0 0 -5db x x x 0 0 1 0 1 -6.25db x x x 0 0 1 1 0 -7.5db x x x 0 0 1 1 1 -8.75db x x x 0 1 0 0 0 -10db x x x 0 1 0 0 1 -11.25db x x x 0 1 0 1 0 -12.5db x x x 0 1 0 1 1 -13.75db x x x 0 1 1 0 0 -15db x x x 0 1 1 0 1 -16.25db x x x 0 1 1 1 0 -17.5db x x x 0 1 1 1 1 -18.75db x x x 1 d3 d2 d1 d0 loudness off (1) 1. if the loudness is switched off, the loudness stage is acting like a volume attenuator with flat frequency response. d0 to d3 determine the attenuation level. table 9. mute msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 1 soft mute on 0 1 soft mute with fast slope (i = i max ) 1 1 soft mute with slow slope (i = i min ) 1 direct mute 0 1 zero crossing mute on 0 0 zero crossing mute off (delayed until next zerocrossing) 1 zero crossing mute and pause detector reset 0 0 160mv zc window threshold (win = 00)
tda7342 software specification 15/20 an additional direct mute function is included in the speaker attenuators. for example an attenuation of 25db on a sele cted output is given by: x x x1 0 1 0 0 0 1 80mv zc window threshold (win = 01) 1 0 40mv zc window threshold (win = 10) 1 1 20mv zc window threshold (win = 11) 0 nonsymmetrical bass cut (1) 1 symmetrical bass cut 1. bass cut for very low frequencies; should not be used at +16 and +18db bass boost (dc gain) table 10. speaker attenuators ( lf, lr, rf, rr) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 1.25db step x x x 0 0 0 0db x x x 0 0 1 -1.25db x x x 0 1 0 -2.5db x x x 0 1 1 -3.75db x x x 1 0 0 -5db x x x 1 0 1 -6.25db x x x 1 1 0 -7.5db x x x 1 1 1 -8.75db 10db step x x x 0 0 0db x x x 0 1 -10db x x x 1 0 -20db x x x 1 1 -30db x x x 1 1 1 1 1 speaker mute table 11. bass/treble msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 treble step 0 0 0 0 -14db 0 0 0 1 -12db table 9. mute (continued) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0
software specification tda7342 16/20 for example 12db treble and -8db bass give the following data byte: 0 0 1 1 1 0 0 1 0 0 1 0 -10db 0 0 1 1 -8db 0 1 0 0 -6db 0 1 0 1 -4db 0 1 1 0 -2db 0 1 1 1 0db 1 1 1 1 0db 1 1 1 0 2db 1 1 0 1 4db 1 1 0 0 6db 1 0 1 1 8db 1 0 1 0 10db 1 0 0 1 12db 1 0 0 0 14db bass steps 0 0 1 0 -10db 0 0 1 1 -8db 0 1 0 0 -6db 0 1 0 1 -4db 0 1 1 0 -2db 0 1 1 1 -0db 1 1 1 1 -0db 1 1 1 0 2db 1 1 0 1 4db 1 1 0 0 6db 1 0 1 1 8db 1 0 1 0 10db 1 0 0 1 12db 1 0 0 0 14db 0 0 0 1 146b 0 0 0 0 18db table 11. bass/treble (continued) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0
tda7342 software specification 17/20 for example to select -47.81db volume the data byte is: 1 1 0 1 1 0 0 1 power on reset: all bytes set to 1 1 1 1 1 1 1 0 table 12. volume msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0.31db fine attenuation steps 0 0 0db 0 1 -0.31db 1 0 -0.62db 1 1 -0.94db 1.25db coarse attenuation steps 0 0 0 0db 0 0 1 -1.25db 0 1 0 -2.5db 0 1 1 -3.75db 1 0 0 -5db 1 0 1 -6.25db 1 1 0 -7.5db 1 1 1 -8.75db 10db gain / attenuation steps 0 0 0 20db 0 0 1 10db 0 1 0 0db 0 1 1 -10db 1 0 0 -20db 1 0 1 -30db 1 1 0 -40db 1 1 1 -50db
package information tda7342 18/20 5 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 7. lqfp32 mechanical data & package dimensions outline and mechanical data 0060661 d dim. mm inch min. typ. max. min. typ. max. a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.600 0.2205 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.600 0.2205 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 3.500 7.000 0.1378 0.2756 ccc 0.100 0.0039 lqfp32 (7 x 7 x 1.40mm) weight: 0.20gr
tda7342 revision history 19/20 6 revision history table 13. document revision history date revision changes 24-jan-2006 1 initial release. 20-nov-2006 2 layout changes, text modifications, updated package informations. 24-sep-2013 3 updated disclaimer.
tda7342 20/20 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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